/*
 *    Based on code from Cortina Systems, Inc.
 *
 *    Copyright (C) 2011, 2012 by Cortina Systems, Inc.
 *    Copyright (C) 2011, 2012 Cavium, Inc.
 *
 *    This program is free software; you can redistribute it and/or modify
 *    it under the terms of the GNU General Public License as published by
 *    the Free Software Foundation; either version 2 of the License, or
 *    (at your option) any later version.
 *
 *    This program is distributed in the hope that it will be useful,
 *    but WITHOUT ANY WARRANTY; without even the implied warranty of
 *    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 *    GNU General Public License for more details.
 *
 */
#define CS4321_GLOBAL_CHIP_ID_LSB			0x0
#define CS4321_GLOBAL_CHIP_ID_MSB			0x1
#define CS4321_GLOBAL_SCRATCH				0x2
#define CS4321_GLOBAL_UCODE_VERSION_LRM			0x3
#define CS4321_GLOBAL_UCODE_VERSION_SR			0x4
#define CS4321_GLOBAL_UCODE_VERSION_CX1			0x5
#define CS4321_GLOBAL_UCODE_VERSION_SMF			0x6
#define CS4321_GLOBAL_UCODE_VERSION_ZR			0x7
#define CS4321_GLOBAL_UCODE_TIMESTAMP0			0x8
#define CS4321_GLOBAL_UCODE_TIMESTAMP1			0x9
#define CS4321_GLOBAL_UCODE_TIMESTAMP2			0xA
#define CS4321_GLOBAL_INGRESS_SOFT_RESET		0xC
#define CS4321_GLOBAL_EGRESS_SOFT_RESET			0xD
#define CS4321_GLOBAL_REF_SOFT_RESET			0xE
#define CS4321_GLOBAL_MPIF_SOFT_RESET			0xF
#define CS4321_GLOBAL_MPIF_RESET_DOTREG			0x10
#define CS4321_GLOBAL_GIGEPCS_SOFT_RESET		0x11
#define CS4321_GLOBAL_INGRESS_FUNCEN			0x12
#define CS4321_GLOBAL_EGRESS_FUNCEN			0x13
#define CS4321_GLOBAL_HOST_MULTILANE_FUNCEN		0x14
#define CS4321_GLOBAL_INGRESS_CLKEN			0x15
#define CS4321_GLOBAL_INGRESS_CLKEN2			0x16
#define CS4321_GLOBAL_EGRESS_CLKEN			0x17
#define CS4321_GLOBAL_EGRESS_CLKEN2			0x18
#define CS4321_GLOBAL_HOST_MULTILANE_CLKSEL		0x19
#define CS4321_GLOBAL_DWNLD_CHECKSUM_CTRL		0x1C
#define CS4321_GLOBAL_DWNLD_CHECKSUM_STATUS		0x1D
#define CS4321_GLOBAL_DWNLD_CHECKSUM_HW			0x1E
#define CS4321_GLOBAL_DWNLD_CHECKSUM_SW			0x1F
#define CS4321_GLOBAL_MSEQCLKCTRL			0x20
#define CS4321_GLOBAL_WATCHDOG_TIMER1			0x23
#define CS4321_GLOBAL_WATCHDOG_TIMER0			0x24
#define CS4321_GLOBAL_PIN_STATUS			0x25
#define CS4321_GLOBAL_GT_10KHZ_REF_CLK_CNT1		0x2D
#define CS4321_GLOBAL_GT_10KHZ_REF_CLK_CNT0		0x2E
#define CS4321_GLOBAL_MISC_CONFIG			0x33
#define CS4321_GLOBAL_SCRATCH0				0x34
#define CS4321_GLOBAL_SCRATCH7				0x3B
#define CS4321_GLOBAL_SYNCE_PRI				0x3C
#define CS4321_GLOBAL_SYNCE_SEC				0x3D
#define CS4321_GLOBAL_LINE_PRBS_CHK_TIMER		0x3E
#define CS4321_GLOBAL_HOST_PRBS_CHK_TIMER		0x3F
#define CS4321_GLOBAL_HOST_ML_PRBS_CHK_TIMER		0x40
#define CS4321_GLOBAL_PRBS_CHK_TIMER_STATUS		0x41
#define CS4321_GLOBAL_GLOBAL_INTERRUPT			0x51
#define CS4321_GLOBAL_GLOBAL_INTE			0x52
#define CS4321_GLOBAL_INGRESS_INTERRUPT			0x54
#define CS4321_GLOBAL_INGRESS_INTE			0x55
#define CS4321_GLOBAL_EGRESS_INTERRUPT			0x57
#define CS4321_GLOBAL_EGRESS_INTE			0x58
#define CS4321_GLOBAL_MISC_INTERRUPT			0x5A
#define CS4321_GLOBAL_MISC_INTE				0x5B
#define CS4321_GPIO_GPIO1				0x100
#define CS4321_GPIO_GPIO1_OUTPUT_CFG			0x101
#define CS4321_GPIO_GPIO1_DRIVE				0x102
#define CS4321_GPIO_GPIO1_VALUE				0x103
#define CS4321_GPIO_GPIO1_TOGGLE			0x104
#define CS4321_GPIO_GPIO1_DELAY				0x105
#define CS4321_GPIO_GPIO2				0x106
#define CS4321_GPIO_GPIO2_OUTPUT_CFG			0x107
#define CS4321_GPIO_GPIO2_DRIVE				0x108
#define CS4321_GPIO_GPIO2_VALUE				0x109
#define CS4321_GPIO_GPIO2_TOGGLE			0x10A
#define CS4321_GPIO_GPIO2_DELAY				0x10B
#define CS4321_GPIO_GPIO3	       			0x10C
#define CS4321_GPIO_GPIO3_OUTPUT_CFG			0x10D
#define CS4321_GPIO_GPIO3_DRIVE				0x10E
#define CS4321_GPIO_GPIO3_VALUE				0x10F
#define CS4321_GPIO_GPIO3_TOGGLE			0x110
#define CS4321_GPIO_GPIO3_DELAY				0x111
#define CS4321_GPIO_GPIO4	       			0x112
#define CS4321_GPIO_GPIO4_OUTPUT_CFG			0x113
#define CS4321_GPIO_GPIO4_DRIVE				0x114
#define CS4321_GPIO_GPIO4_VALUE				0x115
#define CS4321_GPIO_GPIO4_TOGGLE			0x116
#define CS4321_GPIO_GPIO4_DELAY				0x117
#define CS4321_GPIO_GPIO5	       			0x118
#define CS4321_GPIO_GPIO5_OUTPUT_CFG			0x119
#define CS4321_GPIO_GPIO5_DRIVE				0x11a
#define CS4321_GPIO_GPIO5_VALUE				0x11b
#define CS4321_GPIO_GPIO5_TOGGLE			0x11c
#define CS4321_GPIO_GPIO5_DELAY				0x11d
#define CS4321_GPIO_GPIO6	       			0x11e
#define CS4321_GPIO_GPIO6_OUTPUT_CFG			0x11f
#define CS4321_GPIO_GPIO6_DRIVE				0x120
#define CS4321_GPIO_GPIO6_VALUE				0x121
#define CS4321_GPIO_GPIO6_TOGGLE			0x122
#define CS4321_GPIO_GPIO6_DELAY				0x123
#define CS4321_GPIO_GPIO7	       			0x124
#define CS4321_GPIO_GPIO7_OUTPUT_CFG			0x125
#define CS4321_GPIO_GPIO7_DRIVE				0x126
#define CS4321_GPIO_GPIO7_VALUE				0x127
#define CS4321_GPIO_GPIO7_TOGGLE			0x128
#define CS4321_GPIO_GPIO7_DELAY				0x129
#define CS4321_GPIO_GPIO8	       			0x12a
#define CS4321_GPIO_GPIO8_OUTPUT_CFG			0x12b
#define CS4321_GPIO_GPIO8_DRIVE				0x12c
#define CS4321_GPIO_GPIO8_VALUE				0x12d
#define CS4321_GPIO_GPIO8_TOGGLE			0x12e
#define CS4321_GPIO_GPIO8_DELAY				0x12f
#define CS4321_GPIO_GPIO9	       			0x130
#define CS4321_GPIO_GPIO9_OUTPUT_CFG			0x131
#define CS4321_GPIO_GPIO9_DRIVE				0x132
#define CS4321_GPIO_GPIO9_VALUE				0x133
#define CS4321_GPIO_GPIO9_TOGGLE			0x134
#define CS4321_GPIO_GPIO9_DELAY				0x135
#define CS4321_GPIO_GPIO10				0x136
#define CS4321_GPIO_GPIO10_OUTPUT_CFG			0x137
#define CS4321_GPIO_GPIO10_DRIVE			0x138
#define CS4321_GPIO_GPIO10_VALUE			0x139
#define CS4321_GPIO_GPIO10_TOGGLE			0x13a
#define CS4321_GPIO_GPIO10_DELAY			0x13b
#define CS4321_GPIO_GPIO11				0x13c
#define CS4321_GPIO_GPIO11_OUTPUT_CFG			0x13d
#define CS4321_GPIO_GPIO11_DRIVE			0x13e
#define CS4321_GPIO_GPIO11_VALUE			0x13f
#define CS4321_GPIO_GPIO11_TOGGLE			0x140
#define CS4321_GPIO_GPIO11_DELAY			0x141
#define CS4321_GPIO_GPIO12				0x142
#define CS4321_GPIO_GPIO12_OUTPUT_CFG			0x143
#define CS4321_GPIO_GPIO12_DRIVE			0x144
#define CS4321_GPIO_GPIO12_VALUE			0x145
#define CS4321_GPIO_GPIO12_TOGGLE			0x146
#define CS4321_GPIO_GPIO12_DELAY			0x147
#define CS4321_GPIO_GPIO13				0x148
#define CS4321_GPIO_GPIO13_OUTPUT_CFG			0x149
#define CS4321_GPIO_GPIO13_DRIVE			0x14a
#define CS4321_GPIO_GPIO13_VALUE			0x14b
#define CS4321_GPIO_GPIO13_TOGGLE			0x14c
#define CS4321_GPIO_GPIO13_DELAY			0x14d
#define CS4321_GPIO_GPIO14				0x14e
#define CS4321_GPIO_GPIO14_OUTPUT_CFG			0x14f
#define CS4321_GPIO_GPIO14_DRIVE			0x150
#define CS4321_GPIO_GPIO14_VALUE			0x151
#define CS4321_GPIO_GPIO14_TOGGLE			0x152
#define CS4321_GPIO_GPIO14_DELAY			0x153
#define CS4321_GPIO_GPIO15				0x154
#define CS4321_GPIO_GPIO15_OUTPUT_CFG			0x155
#define CS4321_GPIO_GPIO15_DRIVE			0x156
#define CS4321_GPIO_GPIO15_VALUE			0x157
#define CS4321_GPIO_GPIO15_TOGGLE			0x158
#define CS4321_GPIO_GPIO15_DELAY			0x159
#define CS4321_GPIO_GPIO_INPUT1				0x15a
#define CS4321_GPIO_GPIO_INPUT2				0x15b
#define CS4321_GPIO_GPIO_INPUT3				0x15c
#define CS4321_GPIO_GPIO_INPUT4				0x15d
#define CS4321_GPIO_GPIO_INPUT5				0x15e
#define CS4321_GPIO_GPIO_INPUT6				0x15f
#define CS4321_GPIO_GPIO_INPUT7				0x160
#define CS4321_GPIO_GPIO_INPUT8				0x161
#define CS4321_GPIO_GPIO_INPUT9				0x162
#define CS4321_GPIO_GPIO_INPUT10			0x163
#define CS4321_GPIO_GPIO_INPUT11			0x164
#define CS4321_GPIO_GPIO_CFG				0x165
#define CS4321_GPIO_GPIO_INT_POLARITY			0x166
#define CS4321_GPIO_GPIO_INPUT_INT			0x167
#define CS4321_GPIO_GPIO_INPUT_INTE			0x168
#define CS4321_GPIO_GPIO_INPUT_INTS			0x169
#define CS4321_GPIO_GPIO_INPUT_INTZ			0x16A
#define CS4321_GPIO_GPIO_INT				0x16B
#define CS4321_GPIO_GPIO_INTE				0x16C
#define CS4321_GPIO_GPIO_INTS				0x16D
#define CS4321_GPIO_GPIO_INTZ				0x16E
#define CS4321_MSEQ_GRAM_CR				0x200
#define CS4321_MSEQ_GRAM_D1				0x201
#define CS4321_MSEQ_GRAM_D0				0x202
#define CS4321_MSEQ_ENABLE_LSB				0x203
#define CS4321_MSEQ_ENABLE_MSB				0x204
#define CS4321_MSEQ_SERDES_PARAM_LSB			0x205
#define CS4321_MSEQ_POWER_DOWN_LSB			0x208
#define CS4321_MSEQ_POWER_DOWN_MSB			0x209
#define CS4321_MSEQ_STATUS				0x20A
#define CS4321_MSEQ_LEAK_INTERVAL_FFE			0x21C
#define CS4321_MSEQ_COEF_DSP_DRIVE128			0x21F
#define CS4321_MSEQ_COEF_INIT_SEL			0x223
#define CS4321_MSEQ_COEF16_CURRENT_SEL			0x227
#define CS4321_MSEQ_CAL_RX_EQADJ			0x22A
#define CS4321_MSEQ_CAL_RX_PGA				0x22B
#define CS4321_MSEQ_CAL_RX_PHSEL			0x22C
#define CS4321_MSEQ_CAL_RX_SLICER			0x22D
#define CS4321_MSEQ_CAL_RX_DFE_EQ			0x22E
#define CS4321_MSEQ_CAL_RX_AGC_GAIN			0x22F
#define CS4321_MSEQ_SNRAVGSUM0				0x234
#define CS4321_MSEQ_PC_SHADOW				0x236
#define CS4321_MSEQ_OPTIONS_SHADOW			0x237
#define CS4321_MSEQ_OPTIONS				0x240
#define CS4321_MSEQ_PC					0x243
#define CS4321_MSEQ_BANKSELECT				0x24F
#define CS4321_MSEQ_RESET_COUNT_LSB			0x250
#define CS4321_MSEQ_COEF8_FFE0_MSB			0x253
#define CS4321_MSEQ_COEF8_FFE1_LSB			0x254
#define CS4321_MSEQ_COEF8_FFE5_LSB			0x25C
#define CS4321_MSEQ_COEF8_DFE0_LSB			0x260
#define CS4321_MSEQ_COEF8_DFE1_LSB			0x262
#define CS4321_MSEQ_SPARE2_LSB				0x270
#define CS4321_MSEQ_SPARE3_LSB				0x272
#define CS4321_MSEQ_SPARE4_LSB				0x274
#define CS4321_MSEQ_SPARE5_LSB				0x276
#define CS4321_MSEQ_SPARE6_LSB				0x278
#define CS4321_MSEQ_SPARE6_MSB				0x279
#define CS4321_MSEQ_SPARE7_LSB				0x27A
#define CS4321_MSEQ_SPARE8_LSB				0x27C
#define CS4321_MSEQ_SPARE9_LSB				0x27E
#define CS4321_MSEQ_SPARE11_LSB				0x282
#define CS4321_MSEQ_SPARE15_LSB				0x28A
#define CS4321_MSEQ_SPARE17_LSB				0x28E
#define CS4321_MSEQ_SPARE21_LSB				0x296
#define CS4321_MSEQ_SPARE23_LSB				0x29A
#define CS4321_MSEQ_SPARE_LOCAL_TIMING_MSB		0x2A5
#define CS4321_DSP_SDS_DSP_PRECODEDINITFFE21		0x30A
#define CS4321_DSP_SDS_DSP_COEF_DFE0_SELECT		0x37B
#define CS4321_DSP_SDS_DSP_COEF_LARGE_LEAK		0x382
#define CS4321_DSP_SDS_AGC_RX_AGC_DAC_OVRD		0x3D2
#define CS4321_DSP_SDS_AGC_RX_AGC_LOS_STATUS_0	       	0x3DB
#define CS4321_DSP_SDS_AGC_RX_AGC_LOS_STATUS_1		0x3DC
#define CS4321_DSP_SDS_SERDES_SRX_DAC_ENABLEB_LSB	0x400
#define CS4321_DSP_SDS_SERDES_SRX_DAC_ENABLEB_MSB	0x401
#define CS4321_DSP_SDS_SERDES_SRX_DAC_BIAS_SELECT0_MSB	0x403
#define CS4321_DSP_SDS_SERDES_SRX_DAC_BIAS_SELECT1_MSB	0x405
#define CS4321_DSP_SDS_SERDES_SRX_FFE_DELAY_CTRL	0x409
#define CS4321_DSP_SDS_SERDES_SRX_FFE_INBUF_CTRL	0x40A
#define CS4321_DSP_SDS_SERDES_SRX_FFE_PGA_CTRL		0x40B
#define CS4321_DSP_SDS_SERDES_SRX_FFE_MISC		0x40C
#define CS4321_DSP_SDS_SERDES_SRX_DFE0_SELECT		0x40E
#define CS4321_DSP_SDS_SERDES_SRX_DFE_MISC		0x412
#define CS4321_DSP_SDS_SERDES_SRX_AGC_MISC		0x413
#define CS4321_DSP_SDS_TEMPMON_MON_CONTROL0		0x440
#define CS4321_DSP_SDS_TEMPMON_MON_CONTROL1		0x441
#define CS4321_DSP_SDS_TEMPMON_MON_STATUS2		0x448
#define CS4321_DSP_SDS_TEMPMON_MON_LUT_RANGE0		0x44F
#define CS4321_DSP_SDS_TEMPMON_MON_LUT_VALUE0		0x45F
#define CS4321_DSP_SDS_VOLTMON_MON_CONTROL0		0x480
#define CS4321_DSP_SDS_VOLTMON_MON_CONTROL1		0x481
#define CS4321_DSP_SDS_VOLTMON_MON_STATUS2		0x488
#define CS4321_DSP_SDS_VOLTMON_MON_LUT_RANGE0		0x48F
#define CS4321_DSP_SDS_VOLTMON_MON_LUT_VALUE0		0x49F
#define CS4321_LINE_SDS_COMMON_SRX0_RX_CONFIG		0x500
#define CS4321_LINE_SDS_COMMON_SRX0_RX_CLKDIV_CTRL	0x501
#define CS4321_LINE_SDS_COMMON_SRX0_RX_LOOP_FILTER	0x503
#define CS4321_LINE_SDS_COMMON_SRX0_RX_CPA		0x504
#define CS4321_LINE_SDS_COMMON_SRX0_RX_CPB		0x505
#define CS4321_LINE_SDS_COMMON_SRX0_RX_VCO_CTRL		0x507
#define CS4321_LINE_SDS_COMMON_SRX0_RX_MISC		0x509
#define CS4321_LINE_SDS_COMMON_SRX0_RX_SPARE		0x50C
#define CS4321_LINE_SDS_COMMON_SRX0_RX_CONFIG_EYEMON	0x50D
#define CS4321_LINE_SDS_COMMON_SRX0_RX_CONFIG_EYEMON2	0x50E
#define CS4321_LINE_SDS_COMMON_RXVCO0_CONTROL		0x512
#define CS4321_LINE_SDS_COMMON_RXVCO0_STATUS		0x513
#define CS4321_LINE_SDS_COMMON_RXLOCKD0_INTERRUPT	0x51F
#define CS4321_LINE_SDS_COMMON_RXLOCKD0_INTSTATUS	0x520
#define CS4321_LINE_SDS_COMMON_STX0_TX_OUTPUT_CTRLA	0x529
#define CS4321_LINE_SDS_COMMON_STX0_TX_OUTPUT_CTRLB	0x52A
#define CS4321_LINE_SDS_COMMON_STX0_TX_CONFIG_LOCAL_TIMING 0x52B
#define CS4321_LINE_SDS_COMMON_STXP0_TX_CONFIG		0x52C
#define CS4321_LINE_SDS_COMMON_STXP0_TX_PWRDN		0x52D
#define CS4321_LINE_SDS_COMMON_STXP0_TX_CLKOUT_CTRL	0x52F
#define CS4321_LINE_SDS_COMMON_STXP0_TX_LOOP_FILTER	0x530
#define CS4321_LINE_SDS_COMMON_STXP0_TX_CP		0x531
#define CS4321_LINE_SDS_COMMON_TXVCO0_CONTROL		0x539
#define CS4321_LINE_SDS_COMMON_TXVCO0_STATUS		0x53A
#define CS4321_LINE_SDS_COMMON_TXLOCKD0_INTERRUPT	0x545
#define CS4321_LINE_SDS_COMMON_TXLOCKD0_INTSTATUS	0x546
#define CS4321_LINE_SDS_COMMON_TXELST0_CONTROL		0x54E
#define CS4321_LINE_SDS_COMMON_PRBSGEN0_CONFIG		0x54F
#define CS4321_LINE_SDS_COMMON_PRBSGEN0_FIXED0_PATTERN2 0x551
#define CS4321_LINE_SDS_COMMON_PRBSCHK0_CONFIG		0x558
#define CS4321_LINE_SDS_COMMON_PRBSCHK0_COUNT1		0x55A
#define CS4321_LINE_SDS_COMMON_PRBSCHK0_COUNT0		0x55B
#define CS4321_LINE_SDS_COMMON_PRBSCHK0_INTERRUPT	0x55C
#define CS4321_LINE_SDS_COMMON_PRBSCHK0_INTSTATUS	0x55D
#define CS4321_LINE_SDS_COMMON_TX0_CONFIG		0x560
#define CS4321_LINE_SDS_COMMON_RX0_CONFIG		0x561
#define CS4321_LINE_SDS_COMMON_FRAC0_RESET		0x562
#define CS4321_LINE_SDS_COMMON_FRAC0_EN			0x563
#define CS4321_LINE_SDS_COMMON_FRAC0_NUMERATOR0		0x564
#define CS4321_LINE_SDS_COMMON_FRAC0_NUMERATOR1		0x565
#define CS4321_LINE_SDS_COMMON_FRAC0_WIDTH		0x566
#define CS4321_LINE_SDS_COMMON_FRAC0_INTDIV		0x567
#define CS4321_LINE_SDS_COMMON_FRAC0_STAGE1_EN		0x569
#define CS4321_LINE_SDS_COMMON_FRAC0_STAGE2_EN		0x56A
#define CS4321_LINE_SDS_COMMON_FRAC0_STAGE3_EN		0x56B
#define CS4321_LINE_SDS_COMMON_FRAC0_STAGE1PRELOAD0	0x56C
#define CS4321_LINE_SDS_COMMON_FRAC0_STAGE1PRELOAD1	0x56D
#define CS4321_LINE_SDS_COMMON_FRAC0_STAGE2PRELOAD0	0x56E
#define CS4321_LINE_SDS_COMMON_FRAC0_STAGE2PRELOAD1	0x56F
#define CS4321_LINE_SDS_COMMON_FRAC0_STAGE3PRELOAD0	0x570
#define CS4321_LINE_SDS_COMMON_FRAC0_STAGE3PRELOAD1	0x571
#define CS4321_LINE_SDS_COMMON_FRAC0_CLKCTRL		0x572
#define CS4321_LINE_SDS_COMMON_FRAC0_DITHER_EN		0x573
#define CS4321_LINE_SDS_COMMON_FRAC0_DITHER_SEL		0x574
#define CS4321_HOST_SDS_COMMON_SRX0_RX_CONFIG		0x600
#define CS4321_HOST_SDS_COMMON_SRX0_RX_CLKDIV_CTRL	0x601
#define CS4321_HOST_SDS_COMMON_SRX0_RX_CLKOUT_CTRL	0x602
#define CS4321_HOST_SDS_COMMON_SRX0_RX_LOOP_FILTER	0x603
#define CS4321_HOST_SDS_COMMON_SRX0_RX_CPA		0x604
#define CS4321_HOST_SDS_COMMON_SRX0_RX_CONFIG_EYEMON	0x60D
#define CS4321_HOST_SDS_COMMON_SRX0_RX_CONFIG_EYEMON2	0x60E
#define CS4321_HOST_SDS_COMMON_SRX0_RX_DAC_CONFIG	0x60F
#define CS4321_HOST_SDS_COMMON_RXVCO0_CONTROL		0x613
#define CS4321_HOST_SDS_COMMON_RXVCO0_STATUS		0x614
#define CS4321_HOST_SDS_COMMON_RXLOCKD0_INTERRUPT	0x620
#define CS4321_HOST_SDS_COMMON_RXLOCKD0_INTSTATUS	0x621
#define CS4321_HOST_SDS_COMMON_STX0_TX_OUTPUT_CTRLA	0x62A
#define CS4321_HOST_SDS_COMMON_STX0_TX_OUTPUT_CTRLB	0x62B
#define CS4321_HOST_SDS_COMMON_STX0_TX_CONFIG_LOCAL_TIMING 0x62C
#define CS4321_HOST_SDS_COMMON_STXP0_TX_CONFIG		0x62D
#define CS4321_HOST_SDS_COMMON_STXP0_TX_PWRDN		0x62E
#define CS4321_HOST_SDS_COMMON_STXP0_TX_CLKDIV_CTRL	0x62F
#define CS4321_HOST_SDS_COMMON_STXP0_TX_CLKOUT_CTRL	0x630
#define CS4321_HOST_SDS_COMMON_STXP0_TX_LOOP_FILTER	0x631
#define CS4321_HOST_SDS_COMMON_STXP0_TX_CP		0x632
#define CS4321_HOST_SDS_COMMON_TXVCO0_CONTROL		0x63A
#define CS4321_HOST_SDS_COMMON_TXVCO0_STATUS		0x63B
#define CS4321_HOST_SDS_COMMON_TXLOCKD0_INTERRUPT	0x646
#define CS4321_HOST_SDS_COMMON_TXLOCKD0_INTSTATUS	0x647
#define CS4321_HOST_SDS_COMMON_TXELST0_CONTROL		0x64F
#define CS4321_HOST_SDS_COMMON_PRBSGEN0_CONFIG		0x650
#define CS4321_HOST_SDS_COMMON_PRBSGEN0_Fixed0_Pattern2 0x652
#define CS4321_HOST_SDS_COMMON_PRBSCHK0_CONFIG		0x659
#define CS4321_HOST_SDS_COMMON_PRBSCHK0_COUNT1		0x65B
#define CS4321_HOST_SDS_COMMON_PRBSCHK0_COUNT0		0x65C
#define CS4321_HOST_SDS_COMMON_PRBSCHK0_INTERRUPT	0x65D
#define CS4321_HOST_SDS_COMMON_PRBSCHK0_INTSTATUS	0x65E
#define CS4321_HOST_SDS_COMMON_TX0_CONFIG		0x661
#define CS4321_HOST_SDS_COMMON_RX0_CONFIG		0x662
#define CS4321_HOST_SDS_COMMON_FRAC0_RESET		0x663
#define CS4321_HOST_SDS_COMMON_FRAC0_EN			0x664
#define CS4321_HOST_SDS_COMMON_FRAC0_NUMERATOR0		0x665
#define CS4321_HOST_SDS_COMMON_FRAC0_NUMERATOR1		0x666
#define CS4321_HOST_SDS_COMMON_FRAC0_WIDTH		0x667
#define CS4321_HOST_SDS_COMMON_FRAC0_INTDIV		0x668
#define CS4321_HOST_SDS_COMMON_FRAC0_1P6G_EN		0x669
#define CS4321_HOST_SDS_COMMON_FRAC0_STAGE1_EN		0x66A
#define CS4321_HOST_SDS_COMMON_FRAC0_STAGE2_EN		0x66B
#define CS4321_HOST_SDS_COMMON_FRAC0_STAGE3_EN		0x66C
#define CS4321_HOST_SDS_COMMON_FRAC0_STAGE1PRELOAD0	0x66D
#define CS4321_HOST_SDS_COMMON_FRAC0_STAGE1PRELOAD1	0x66E
#define CS4321_HOST_SDS_COMMON_FRAC0_STAGE2PRELOAD0	0x66F
#define CS4321_HOST_SDS_COMMON_FRAC0_STAGE2PRELOAD1	0x670
#define CS4321_HOST_SDS_COMMON_FRAC0_STAGE3PRELOAD0	0x671
#define CS4321_HOST_SDS_COMMON_FRAC0_STAGE3PRELOAD1	0x672
#define CS4321_HOST_SDS_COMMON_FRAC0_CLKCTRL		0x673
#define CS4321_HOST_ML_SDS_COMMON_SRX0_RX_CONFIG	0x700
#define CS4321_HOST_ML_SDS_COMMON_SRX0_RX_CLKDIV_CTRL	0x701
#define CS4321_HOST_ML_SDS_COMMON_RXVCO0_CONTROL	0x70F
#define CS4321_HOST_ML_SDS_COMMON_RXVCO0_STATUS		0x710
#define CS4321_HOST_ML_SDS_COMMON_RXLOCKD0_INTERRUPT	0x71B
#define CS4321_HOST_ML_SDS_COMMON_RXLOCKD0_INTSTATUS	0x71C
#define CS4321_HOST_ML_SDS_COMMON_RXLOCKD0_INTENABLE	0x71D
#define CS4321_HOST_ML_SDS_COMMON_STX0_TX_OUTPUT_CTRLA	0x723
#define CS4321_HOST_ML_SDS_COMMON_STX0_TX_OUTPUT_CTRLB	0x724
#define CS4321_HOST_ML_SDS_COMMON_STXP0_TX_CONFIG	0x725
#define CS4321_HOST_ML_SDS_COMMON_STXP0_TX_PWRDN	0x726
#define CS4321_HOST_ML_SDS_COMMON_STXP0_TX_CLKDIV_CTRL	0x727
#define CS4321_HOST_ML_SDS_COMMON_TXVCO0_CONTROL	0x731
#define CS4321_HOST_ML_SDS_COMMON_TXVCO0_STATUS		0x732
#define CS4321_HOST_ML_SDS_COMMON_TXVCO0_INTERRUPT	0x733
#define CS4321_HOST_ML_SDS_COMMON_TXVCO0_INTENABLE	0x735
#define CS4321_HOST_ML_SDS_COMMON_TXLOCKD0_INTERRUPT	0x73D
#define CS4321_HOST_ML_SDS_COMMON_TXLOCKD0_INTSTATUS	0x73E
#define CS4321_HOST_ML_SDS_COMMON_TXLOCKD0_INTENABLE	0x73F
#define CS4321_HOST_ML_SDS_COMMON_PRBSGEN0_CONFIG	0x747
#define CS4321_HOST_ML_SDS_COMMON_PRBSGEN0_Fixed0_Pattern2 0x749
#define CS4321_HOST_ML_SDS_COMMON_PRBSCHK0_CONFIG	0x750
#define CS4321_HOST_ML_SDS_COMMON_PRBSCHK0_COUNT1	0x752
#define CS4321_HOST_ML_SDS_COMMON_PRBSCHK0_COUNT0	0x753
#define CS4321_HOST_ML_SDS_COMMON_PRBSCHK0_INTERRUPT	0x754
#define CS4321_HOST_ML_SDS_COMMON_PRBSCHK0_INTSTATUS	0x755
#define CS4321_HOST_ML_SDS_COMMON_PRBSCHK0_INTENABLE	0x756
#define CS4321_HOST_ML_SDS_COMMON_TX0_CONFIG		0x758
#define CS4321_HOST_ML_SDS_COMMON_RX0_CONFIG		0x759
#define CS4321_HOST_ML_SDS_COMMON_Int			0x75A
#define CS4321_HOST_ML_SDS_COMMON_IntEn			0x75B
#define CS4321_HOST_ML_SDS_COMMON_PRBSCHKi		0x75C
#define CS4321_HOST_ML_SDS_COMMON_PRBSCHKe		0x75D
#define CS4321_HOST_ML_SDS_COMMON_RXVCOi		0x761
#define CS4321_HOST_ML_SDS_COMMON_RXVCOe		0x762
#define CS4321_HOST_ML_SDS_COMMON_RXLOCKDi		0x763
#define CS4321_HOST_ML_SDS_COMMON_RXLOCKDe		0x764
#define CS4321_HOST_ML_SDS_COMMON_TXVCOi		0x768
#define CS4321_HOST_ML_SDS_COMMON_TXVCOe		0x769
#define CS4321_HOST_ML_SDS_COMMON_TXLOCKDi		0x76A
#define CS4321_HOST_ML_SDS_COMMON_TXLOCKDe		0x76B
#define CS4321_AN_TX_AN_COMPLETE_STATUS_INT		0x806
#define CS4321_AN_TX_AN_COMPLETE_STATUS_INTE		0x807
#define CS4321_AN_TX_AN_COMPLETE_STATUS_INTS		0x808
#define CS4321_AN_TX_MAIN_INT				0x82D
#define CS4321_AN_TX_MAIN_INTE				0x82E
#define CS4321_AN_TX_MAIN_INTS				0x82F
#define CS4321_AN_TX_TX_AFIFO_INT			0x831
#define CS4321_AN_TX_TX_AFIFO_INTE			0x832
#define CS4321_AN_TX_TX_AFIFO_INTS			0x833
#define CS4321_AN_RX_MAIN_INT				0x85A
#define CS4321_AN_RX_MAIN_INTE				0x85B
#define CS4321_AN_RX_MAIN_INTS				0x85C
#define CS4321_AN_RX_RX_AFIFO_INT			0x85E
#define CS4321_AN_RX_RX_AFIFO_INTE			0x85F
#define CS4321_AN_RX_RX_AFIFO_INTS			0x860
#define CS4321_TP_TX_TRAINING_INT			0x888
#define CS4321_TP_TX_TRAINING_INTE			0x889
#define CS4321_TP_TX_TRAINING_INTS			0x88A
#define CS4321_KR_FEC_TX_INT				0x90D
#define CS4321_KR_FEC_TX_INTE				0x90E
#define CS4321_KR_FEC_TX_INTO				0x90F
#define CS4321_KR_FEC_RX_INT				0x95F
#define CS4321_KR_FEC_RX_INTE				0x960
#define CS4321_KR_FEC_RX_INTO				0x961
#define CS4321_XGPCS_LINE_TX_TXCNTRL			0xA00
#define CS4321_XGPCS_LINE_TX_TXINT			0xA02
#define CS4321_XGPCS_LINE_TX_TXINTENABLE		0xA03
#define CS4321_XGPCS_LINE_RX_RXCNTRL			0xA20
#define CS4321_XGPCS_LINE_RX_RXSTATUS			0xA22
#define CS4321_XGPCS_LINE_RX_RXINT			0xA23
#define CS4321_XGPCS_LINE_RX_RXINTENABLE		0xA24
#define CS4321_XGPCS_LINE_RX_RXINTZ			0xA25
#define CS4321_XGPCS_HOST_TX_TXCNTRL			0xA80
#define CS4321_XGPCS_HOST_TX_TXINT			0xA82
#define CS4321_XGPCS_HOST_TX_TXINTENABLE		0xA83
#define CS4321_XGPCS_HOST_RX_RXCNTRL			0xAA0
#define CS4321_XGPCS_HOST_RX_RXINT			0xAA3
#define CS4321_XGPCS_HOST_RX_RXINTENABLE		0xAA4
#define CS4321_EGPCS_LINE_RX_MODE			0xB00
#define CS4321_EGPCS_LINE_RX_INTERRUPT			0xB01
#define CS4321_EGPCS_LINE_RX_INTENABLE			0xB02
#define CS4321_EGPCS_LINE_TX_MODE			0xB10
#define CS4321_EGPCS_LINE_TX_INTERRUPT			0xB15
#define CS4321_EGPCS_LINE_TX_INTENABLE			0xB16
#define CS4321_EGPCS_HOST_RX_MODE			0xB80
#define CS4321_EGPCS_HOST_RX_INTERRUPT			0xB81
#define CS4321_EGPCS_HOST_RX_INTENABLE			0xB82
#define CS4321_EGPCS_HOST_TX_MODE			0xB90
#define CS4321_EGPCS_HOST_TX_INTERRUPT			0xB95
#define CS4321_EGPCS_HOST_TX_INTENABLE			0xB96
#define CS4321_GIGEPCS_LINE_CONTROL			0xC00
#define CS4321_GIGEPCS_LINE_STATUS			0xC01
#define CS4321_GIGEPCS_LINE_PHY1			0xC02
#define CS4321_GIGEPCS_LINE_PHY0			0xC03
#define CS4321_GIGEPCS_LINE_DEV_ABILITY			0xC04
#define CS4321_GIGEPCS_LINE_PARTNER_ABILITY		0xC05
#define CS4321_GIGEPCS_LINE_AN_EXPANSION		0xC06
#define CS4321_GIGEPCS_LINE_DEV_NEXT_PAGE		0xC07
#define CS4321_GIGEPCS_LINE_PARTNER_NEXT_PAGE		0xC08
#define CS4321_GIGEPCS_LINE_MASTER_SLAVE_CNTL		0xC09
#define CS4321_GIGEPCS_LINE_MASTER_SLAVE_STAT		0xC0A
#define CS4321_GIGEPCS_LINE_EXTENDED_STATUS		0xC0F
#define CS4321_GIGEPCS_LINE_AUTONEG_TRACE		0xC10
#define CS4321_GIGEPCS_LINE_LINK_TIMER0			0xC12
#define CS4321_GIGEPCS_LINE_LINK_TIMER1			0xC13
#define CS4321_GIGEPCS_LINE_RX_8B10B_DEC_ERR1		0xC15
#define CS4321_GIGEPCS_LINE_RX_8B10B_DEC_ERR0		0xC16
#define CS4321_GIGEPCS_INT_LINE_PCS1GE_INTERRUPT	0xC40
#define CS4321_GIGEPCS_INT_LINE_PCS1GE_INTENABLE	0xC41
#define CS4321_GIGEPCS_INT_LINE_PCS1GE_INTSTATUS	0xC42
#define CS4321_GIGEPCS_INT_LINE_PCS1GE_AUTONEG		0xC43
#define CS4321_GIGEPCS_HOST_CONTROL			0xC80
#define CS4321_GIGEPCS_HOST_STATUS			0xC81
#define CS4321_GIGEPCS_HOST_PHY1			0xC82
#define CS4321_GIGEPCS_HOST_PHY0			0xC83
#define CS4321_GIGEPCS_HOST_DEV_ABILITY			0xC84
#define CS4321_GIGEPCS_HOST_PARTNER_ABILITY		0xC85
#define CS4321_GIGEPCS_HOST_AN_EXPANSION		0xC86
#define CS4321_GIGEPCS_HOST_DEV_NEXT_PAGE		0xC87
#define CS4321_GIGEPCS_HOST_PARTNER_NEXT_PAGE		0xC88
#define CS4321_GIGEPCS_HOST_MASTER_SLAVE_CNTL		0xC89
#define CS4321_GIGEPCS_HOST_MASTER_SLAVE_STAT		0xC8A
#define CS4321_GIGEPCS_HOST_EXTENDED_STATUS		0xC8F
#define CS4321_GIGEPCS_HOST_AUTONEG_TRACE		0xC90
#define CS4321_GIGEPCS_HOST_LINK_TIMER0			0xC92
#define CS4321_GIGEPCS_HOST_LINK_TIMER1			0xC93
#define CS4321_GIGEPCS_HOST_RX_8B10B_DEC_ERR1		0xC95
#define CS4321_GIGEPCS_HOST_RX_8B10B_DEC_ERR0		0xC96
#define CS4321_GIGEPCS_INT_HOST_PCS1GE_INTERRUPT	0xCC0
#define CS4321_GIGEPCS_INT_HOST_PCS1GE_INTENABLE	0xCC1
#define CS4321_GIGEPCS_INT_HOST_PCS1GE_INTSTATUS	0xCC2
#define CS4321_GIGEPCS_INT_HOST_PCS1GE_AUTONEG		0xCC3
#define CS4321_HIF_COMMON_SAMPLEINT			0xD00
#define CS4321_HIF_COMMON_SAMPLEINTENABLE		0xD01
#define CS4321_HIF_COMMON_RXCONTROL0			0xD02
#define CS4321_HIF_COMMON_TXCONTROL0			0xD08
#define CS4321_HIF_COMMON_TXCONTROL3			0xD0B
#define CS4321_HIF_SFI42_RX_RXRISEINT			0xD28
#define CS4321_HIF_SFI42_RX_RXRISEINTENABLE		0xD29
#define CS4321_HIF_SFI42_RX_RXFALLINT			0xD2B
#define CS4321_HIF_SFI42_RX_RXFALLINTENABLE		0xD2C
#define CS4321_HIF_XGXS_COMMON_CONTROL0			0xD30
#define CS4321_HIF_XGXS_TX_TXRISEINT			0xD3B
#define CS4321_HIF_XGXS_TX_TXRISEINTENABLE		0xD3C
#define CS4321_HIF_XGXS_RX_RXRISEINT			0xD49
#define CS4321_HIF_XGXS_RX_RXRISEINTENABLE		0xD4A
#define CS4321_HIF_XGXS_RX_RXFALLINT			0xD4C
#define CS4321_HIF_XGXS_RX_RXFALLINTENABLE		0xD4D
#define CS4321_XGRS_LINE_TX_TXCNTRL			0xE00
#define CS4321_XGRS_LINE_TX_TXINT			0xE03
#define CS4321_XGRS_LINE_TX_TXINTENABLE			0xE04
#define CS4321_XGRS_LINE_RX_RXCNTRL1			0xE10
#define CS4321_XGRS_LINE_RX_RXINT			0xE13
#define CS4321_XGRS_LINE_RX_RXINTENABLE			0xE14
#define CS4321_XGRS_HOST_TX_TXCNTRL			0xE80
#define CS4321_XGRS_HOST_TX_TXINT			0xE83
#define CS4321_XGRS_HOST_TX_TXINTENABLE			0xE84
#define CS4321_XGRS_HOST_RX_RXCNTRL1			0xE90
#define CS4321_XGRS_HOST_RX_RXINT			0xE93
#define CS4321_XGRS_HOST_RX_RXINTENABLE			0xE94
#define CS4321_XGMAC_LINE_RX_CFG_COM			0xF00
#define CS4321_XGMAC_LINE_RX_CFG_RX			0xF01
#define CS4321_XGMAC_LINE_RX_MAXLEN			0xF09
#define CS4321_XGMAC_LINE_RX_MAXLEN_VLAN_UP0		0xF0A
#define CS4321_XGMAC_LINE_RX_MAXLEN_VLAN_UP1		0xF0B
#define CS4321_XGMAC_LINE_RX_MAXLEN_VLAN_UP2		0xF0C
#define CS4321_XGMAC_LINE_RX_MAXLEN_VLAN_UP3		0xF0D
#define CS4321_XGMAC_LINE_RX_MAXLEN_VLAN_UP4		0xF0E
#define CS4321_XGMAC_LINE_RX_MAXLEN_VLAN_UP5		0xF0F
#define CS4321_XGMAC_LINE_RX_MAXLEN_VLAN_UP6		0xF10
#define CS4321_XGMAC_LINE_RX_MAXLEN_VLAN_UP7		0xF11
#define CS4321_XGMAC_LINE_RX_INTERRUPT			0xF16
#define CS4321_XGMAC_LINE_RX_INTENABLE			0xF17
#define CS4321_XGMAC_LINE_RX_INTERRUPTS			0xF19
#define CS4321_XGMAC_LINE_TX_CFG_COM			0xF40
#define CS4321_XGMAC_LINE_TX_CFG_TX			0xF41
#define CS4321_XGMAC_LINE_TX_CFG_TX_IFG			0xF43
#define CS4321_XGMAC_LINE_TX_MAXLEN			0xF4A
#define CS4321_XGMAC_LINE_TX_MAXLEN_VLAN_UP0		0xF4B
#define CS4321_XGMAC_LINE_TX_MAXLEN_VLAN_UP1		0xF4C
#define CS4321_XGMAC_LINE_TX_MAXLEN_VLAN_UP2		0xF4D
#define CS4321_XGMAC_LINE_TX_MAXLEN_VLAN_UP3		0xF4E
#define CS4321_XGMAC_LINE_TX_MAXLEN_VLAN_UP4		0xF4F
#define CS4321_XGMAC_LINE_TX_MAXLEN_VLAN_UP5		0xF50
#define CS4321_XGMAC_LINE_TX_MAXLEN_VLAN_UP6		0xF51
#define CS4321_XGMAC_LINE_TX_MAXLEN_VLAN_UP7		0xF52
#define CS4321_XGMAC_LINE_TX_INTERRUPT			0xF59
#define CS4321_XGMAC_LINE_TX_INTENABLE			0xF5A
#define CS4321_XGMAC_LINE_TX_INTERRUPTS			0xF6A
#define CS4321_XGMAC_HOST_RX_CFG_COM			0xF80
#define CS4321_XGMAC_HOST_RX_CFG_RX			0xF81
#define CS4321_XGMAC_HOST_RX_MAXLEN			0xF89
#define CS4321_XGMAC_HOST_RX_MAXLEN_VLAN_UP0		0xF8A
#define CS4321_XGMAC_HOST_RX_MAXLEN_VLAN_UP1		0xF8B
#define CS4321_XGMAC_HOST_RX_MAXLEN_VLAN_UP2		0xF8C
#define CS4321_XGMAC_HOST_RX_MAXLEN_VLAN_UP3		0xF8D
#define CS4321_XGMAC_HOST_RX_MAXLEN_VLAN_UP4		0xF8E
#define CS4321_XGMAC_HOST_RX_MAXLEN_VLAN_UP5		0xF8F
#define CS4321_XGMAC_HOST_RX_MAXLEN_VLAN_UP6		0xF90
#define CS4321_XGMAC_HOST_RX_MAXLEN_VLAN_UP7		0xF91
#define CS4321_XGMAC_HOST_RX_INTERRUPT			0xF96
#define CS4321_XGMAC_HOST_RX_INTENABLE			0xF97
#define CS4321_XGMAC_HOST_RX_INTERRUPTS			0xF99
#define CS4321_XGMAC_HOST_TX_CFG_COM			0xFC0
#define CS4321_XGMAC_HOST_TX_CFG_TX			0xFC1
#define CS4321_XGMAC_HOST_TX_CFG_TX_IFG			0xFC3
#define CS4321_XGMAC_HOST_TX_MAXLEN			0xFCA
#define CS4321_XGMAC_HOST_TX_MAXLEN_VLAN_UP0		0xFCB
#define CS4321_XGMAC_HOST_TX_MAXLEN_VLAN_UP1		0xFCC
#define CS4321_XGMAC_HOST_TX_MAXLEN_VLAN_UP2		0xFCD
#define CS4321_XGMAC_HOST_TX_MAXLEN_VLAN_UP3		0xFCE
#define CS4321_XGMAC_HOST_TX_MAXLEN_VLAN_UP4		0xFCF
#define CS4321_XGMAC_HOST_TX_MAXLEN_VLAN_UP5		0xFD0
#define CS4321_XGMAC_HOST_TX_MAXLEN_VLAN_UP6		0xFD1
#define CS4321_XGMAC_HOST_TX_MAXLEN_VLAN_UP7		0xFD2
#define CS4321_XGMAC_HOST_TX_INTERRUPT			0xFD9
#define CS4321_XGMAC_HOST_TX_INTENABLE			0xFDA
#define CS4321_XGMAC_HOST_TX_INTERRUPTS			0xFEA
#define CS4321_MACSEC_INGRESS_RESET			0x1000
#define CS4321_MACSEC_INGRESS_DEBUG_FIFO_ACCESS		0x1002
#define CS4321_MACSEC_INGRESS_DEBUG_FIFO_DATA0		0x1006
#define CS4321_MACSEC_INGRESS_DEBUG_FIFO_CTX		0x1007
#define CS4321_MACSEC_INGRESS_LB_FIFO_OUTPUT		0x1008
#define CS4321_MACSEC_INGRESS_LB_FIFO_IPG		0x1009
#define CS4321_MACSEC_INGRESS_LB_FIFO_ACCESS		0x100A
#define CS4321_MACSEC_INGRESS_LB_FIFO_DATA3		0x100B
#define CS4321_MACSEC_INGRESS_LB_FIFO_DATA2		0x100C
#define CS4321_MACSEC_INGRESS_LB_FIFO_DATA1		0x100D
#define CS4321_MACSEC_INGRESS_LB_FIFO_DATA0		0x100E
#define CS4321_MACSEC_INGRESS_LB_FIFO_INFO		0x100F
#define CS4321_MACSEC_INGRESS_LB_FIFO_CTX		0x1010
#define CS4321_MACSEC_INGRESS_CTX_MEM0			0x1200
#define CS4321_MACSEC_INGRESS_CORE_HOST0		0x1400
#define CS4321_MACSEC_INGRESS_TCAM0			0x1600
#define CS4321_MACSEC_INGRESS_TCAM_MASK11		0x1800
#define CS4321_MACSEC_INGRESS_TCAM_ENTRY_0_MASK		0x180C
#define CS4321_MACSEC_INGRESS_TCAM_ENTRY_VALID_15_0	0x182C
#define CS4321_MACSEC_INGRESS_TCAM_ENTRY_VALID_16	0x182D
#define CS4321_MACSEC_INGRESS_TCAM_ENTRY_INVERT_15_0	0x182E
#define CS4321_MACSEC_INGRESS_TCAM_ENTRY_INVERT_16	0x182F
#define CS4321_MACSEC_INGRESS_TOKEN_MEM0		0x1900
#define CS4321_MACSEC_INGRESS_CC_TCAM0			0x1A00
#define CS4321_MACSEC_INGRESS_CC_TCAM_MASK2		0x1A40
#define CS4321_MACSEC_INGRESS_CC_TCAM_ENTRY_VALID	0x1A43
#define CS4321_MACSEC_INGRESS_CC_TCAM_ENTRY_INVERT	0x1A44
#define CS4321_MACSEC_INGRESS_CC_TCAM_ENTRY_0_MASK	0x1A46
#define CS4321_MACSEC_INGRESS_TAG_CONTROL		0x1A56
#define CS4321_MACSEC_INGRESS_R802DOT1S_TAG_ET0		0x1A57
#define CS4321_MACSEC_INGRESS_R802DOT1S_TAG_ET1		0x1A58
#define CS4321_MACSEC_INGRESS_R802DOT1S_TAG_ET2		0x1A59
#define CS4321_MACSEC_INGRESS_STCAM_INVALID_FRAME_TOKEN5		0x1A5A
#define CS4321_MACSEC_INGRESS_STCAM_INVALID_FRAME_TOKEN0		0x1A5F
#define CS4321_MACSEC_INGRESS_UNCONTROLLED_FRAME_STCAM_MISS_TOKEN5	0x1A60
#define CS4321_MACSEC_INGRESS_UNCONTROLLED_FRAME_STCAM_MISS_TOKEN0	0x1A65
#define CS4321_MACSEC_INGRESS_CONTROLLED_FRAME_STCAM_MISS_TOKEN5	0x1A66
#define CS4321_MACSEC_INGRESS_CONTROLLED_FRAME_STCAM_MISS_TOKEN0	0x1A6B
#define CS4321_MACSEC_INGRESS_CCTCAM_MISS_ACTION			0x1A6C
#define CS4321_MACSEC_INGRESS_CCTCAM_HIT_ACTION_UNCONTROLLED_FRAME	0x1A6D
#define CS4321_MACSEC_INGRESS_CCTCAM_HIT_ACTION_CONTROLLED_FRAME	0x1A6E
#define CS4321_MACSEC_INGRESS_STCAM_SA_MAP5		0x1A73
#define CS4321_MACSEC_INGRESS_LB_FIFO_PKT_CTRL		0x1A79
#define CS4321_MACSEC_INGRESS_DEBUG_FIFO_CTRL		0x1A7A
#define CS4321_MACSEC_INGRESS_DFF_LEVEL			0x1A7C
#define CS4321_MACSEC_INGRESS_DSF_LEVEL			0x1A7E
#define CS4321_MACSEC_INGRESS_DCF_LEVEL			0x1A80
#define CS4321_MACSEC_INGRESS_LB_FIFO_STATUS		0x1A90
#define CS4321_MACSEC_INGRESS_DEBUG_FIFO_THRESHOLD	0x1A91
#define CS4321_MACSEC_INGRESS_DEBUG_FIFO_STATUS		0x1A92
#define CS4321_MACSEC_INGRESS_DEBUG_FIFO_CTX_STATUS	0x1A94
#define CS4321_MACSEC_INGRESS_SHAPER_DELAY		0x1A97
#define CS4321_MACSEC_INGRESS_MAIN_INT			0x1A9C
#define CS4321_MACSEC_INGRESS_MAIN_INTE			0x1A9D
#define CS4321_MACSEC_INGRESS_MAIN_INTS			0x1A9E
#define CS4321_MACSEC_INGRESS_FIFOS_INT			0x1AA0
#define CS4321_MACSEC_INGRESS_FIFOS_INTE		0x1AA1
#define CS4321_MACSEC_INGRESS_FIFOS_INTS		0x1AA2
#define CS4321_MACSEC_INGRESS_IP_FIFO_INT		0x1AA4
#define CS4321_MACSEC_INGRESS_IP_FIFO_INTE		0x1AA5
#define CS4321_MACSEC_INGRESS_IP_FIFO_INTS		0x1AA6
#define CS4321_MACSEC_INGRESS_IP_TOKEN_FIFO_INT		0x1AA8
#define CS4321_MACSEC_INGRESS_IP_TOKEN_FIFO_INTE	0x1AA9
#define CS4321_MACSEC_INGRESS_IP_TOKEN_FIFO_INTS	0x1AAA
#define CS4321_MACSEC_INGRESS_OP_FIFO_INT		0x1AAC
#define CS4321_MACSEC_INGRESS_OP_FIFO_INTE		0x1AAD
#define CS4321_MACSEC_INGRESS_OP_FIFO_INTS		0x1AAE
#define CS4321_MACSEC_INGRESS_ERR_DROP_FIFO_INT		0x1AB0
#define CS4321_MACSEC_INGRESS_ERR_DROP_FIFO_INTE	0x1AB1
#define CS4321_MACSEC_INGRESS_ERR_DROP_FIFO_INTS	0x1AB2
#define CS4321_MACSEC_INGRESS_I_PPR_FIFO_INT		0x1AB4
#define CS4321_MACSEC_INGRESS_I_PPR_FIFO_INTE		0x1AB5
#define CS4321_MACSEC_INGRESS_I_PPR_FIFO_INTS		0x1AB6
#define CS4321_MACSEC_INGRESS_LB_FIFO_INT		0x1ABC
#define CS4321_MACSEC_INGRESS_LB_FIFO_INTE		0x1ABD
#define CS4321_MACSEC_INGRESS_LB_FIFO_INTS		0x1ABE
#define CS4321_MACSEC_INGRESS_LB_FIFO_SYNC_INT		0x1AC0
#define CS4321_MACSEC_INGRESS_LB_FIFO_SYNC_INTE		0x1AC1
#define CS4321_MACSEC_INGRESS_LB_FIFO_SYNC_INTS		0x1AC2
#define CS4321_MACSEC_INGRESS_LB_FIFO_MEM_INT		0x1AC4
#define CS4321_MACSEC_INGRESS_LB_FIFO_MEM_INTE		0x1AC5
#define CS4321_MACSEC_INGRESS_LB_FIFO_MEM_INTS		0x1AC6
#define CS4321_MACSEC_INGRESS_CTX_MEM_INT		0x1AC8
#define CS4321_MACSEC_INGRESS_CTX_MEM_INTE		0x1AC9
#define CS4321_MACSEC_INGRESS_CTX_MEM_INTS		0x1ACA
#define CS4321_MACSEC_INGRESS_DEBUG_FIFO_INT		0x1ACC
#define CS4321_MACSEC_INGRESS_DEBUG_FIFO_INTE		0x1ACD
#define CS4321_MACSEC_INGRESS_DEBUG_FIFO_INTS		0x1ACE
#define CS4321_MACSEC_INGRESS_DEBUG_FIFO_MEM_INT	0x1AD0
#define CS4321_MACSEC_INGRESS_DEBUG_FIFO_MEM_INTE	0x1AD1
#define CS4321_MACSEC_INGRESS_DEBUG_FIFO_MEM_INTS	0x1AD2
#define CS4321_MACSEC_INGRESS_DEBUG_FIFO_CTX_INT	0x1AD4
#define CS4321_MACSEC_INGRESS_DEBUG_FIFO_CTX_INTE	0x1AD5
#define CS4321_MACSEC_INGRESS_DEBUG_FIFO_CTX_INTS	0x1AD6
#define CS4321_MACSEC_INGRESS_LB_FIFO_CTX_INT		0x1AD8
#define CS4321_MACSEC_INGRESS_LB_FIFO_CTX_INTE		0x1AD9
#define CS4321_MACSEC_INGRESS_LB_FIFO_CTX_INTS		0x1ADA
#define CS4321_MACSEC_INGRESS_TOKEN_MEM_INT		0x1ADC
#define CS4321_MACSEC_INGRESS_TOKEN_MEM_INTE		0x1ADD
#define CS4321_MACSEC_INGRESS_TOKEN_MEM_INTS		0x1ADE
#define CS4321_MACSEC_INGRESS_CLAUSE912_FAIL_INT	0x1AE1
#define CS4321_MACSEC_INGRESS_CLAUSE912_FAIL_INTE	0x1AE2
#define CS4321_MACSEC_INGRESS_CLAUSE912_FAIL_INTS	0x1AE3
#define CS4321_MACSEC_INGRESS_CLASSIFIER_ERROR_INT	0x1AE5
#define CS4321_MACSEC_INGRESS_CLASSIFIER_ERROR_INTE	0x1AE6
#define CS4321_MACSEC_INGRESS_CLASSIFIER_ERROR_INTS	0x1AE7
#define CS4321_MACSEC_INGRESS_CCT_FIFO_INT		0x1AE9
#define CS4321_MACSEC_INGRESS_CCT_FIFO_INTE		0x1AEA
#define CS4321_MACSEC_INGRESS_CCT_FIFO_INTS		0x1AEB
#define CS4321_MACSEC_INGRESS_DF_FIFO_INT		0x1AED
#define CS4321_MACSEC_INGRESS_DF_FIFO_INTE		0x1AEE
#define CS4321_MACSEC_INGRESS_DF_FIFO_INTS		0x1AEF
#define CS4321_MACSEC_INGRESS_DS_FIFO_INT		0x1AF1
#define CS4321_MACSEC_INGRESS_DS_FIFO_INTE		0x1AF2
#define CS4321_MACSEC_INGRESS_DS_FIFO_INTS		0x1AF3
#define CS4321_MACSEC_INGRESS_DC_FIFO_INT		0x1AF5
#define CS4321_MACSEC_INGRESS_DC_FIFO_INTE		0x1AF6
#define CS4321_MACSEC_INGRESS_DC_FIFO_INTS		0x1AF7
#define CS4321_MACSEC_INGRESS_SHAPER_FIFO_INT		0x1AF9
#define CS4321_MACSEC_INGRESS_SHAPER_FIFO_INTE		0x1AFA
#define CS4321_MACSEC_INGRESS_SHAPER_FIFO_INTS		0x1AFB
#define CS4321_MACSEC_INGRESS_CLAUSE912_CONFIG		0x1AFD
#define CS4321_MACSEC_INGRESS_STCAM_ILLEGAL_FRAME_TOKEN5 0x1AFF
#define CS4321_MACSEC_INGRESS_STCAM_ILLEGAL_FRAME_TOKEN0 0x1B04
#define CS4321_MACSEC_INGRESS_CONTROL_VALID_0		0x1B05
#define CS4321_MACSEC_INGRESS_CONTROL_VALID_1		0x1B06
#define CS4321_MACSEC_INGRESS_CONTROL_0_DA2		0x1B07
#define CS4321_MACSEC_INGRESS_CONTROL_0_ET		0x1B1F
#define CS4321_MACSEC_INGRESS_CONTROL_DA_RANGE_LOW2	0x1B27
#define CS4321_MACSEC_INGRESS_CONTROL_DA_RANGE_HIGH2	0x1B2A
#define CS4321_MACSEC_INGRESS_CONTROL_0_DA_ET3		0x1B2D
#define CS4321_MACSEC_INGRESS_CONTROL_1_DA_ET3		0x1B31
#define CS4321_MACSEC_EGRESS_RESET			0x2200
#define CS4321_MACSEC_EGRESS_DEBUG_FIFO_ACCESS		0x2202
#define CS4321_MACSEC_EGRESS_DEBUG_FIFO_DATA0		0x2206
#define CS4321_MACSEC_EGRESS_DEBUG_FIFO_CTX		0x2207
#define CS4321_MACSEC_EGRESS_CTX_MEM0			0x2400
#define CS4321_MACSEC_EGRESS_CORE_HOST0			0x2600
#define CS4321_MACSEC_EGRESS_TCAM0			0x2700
#define CS4321_MACSEC_EGRESS_TCAM_MASK7			0x2800
#define CS4321_MACSEC_EGRESS_TCAM_ENTRY_0_MASK		0x2808
#define CS4321_MACSEC_EGRESS_TCAM_ENTRY_VALID_15_0	0x2828
#define CS4321_MACSEC_EGRESS_TCAM_ENTRY_VALID_16	0x2829
#define CS4321_MACSEC_EGRESS_TCAM_ENTRY_INVERT_15_0	0x282A
#define CS4321_MACSEC_EGRESS_TCAM_ENTRY_INVERT_16	0x282B
#define CS4321_MACSEC_EGRESS_TOKEN_MEM0			0x2900
#define CS4321_MACSEC_EGRESS_TAG_CONTROL		0x2A00
#define CS4321_MACSEC_EGRESS_R802DOT1S_TAG_ET0		0x2A03
#define CS4321_MACSEC_EGRESS_R802DOT1S_TAG_ET1		0x2A04
#define CS4321_MACSEC_EGRESS_R802DOT1S_TAG_ET2		0x2A05
#define CS4321_MACSEC_EGRESS_STCAM_MISS_TOKEN5		0x2A06
#define CS4321_MACSEC_EGRESS_STCAM_MISS_TOKEN0		0x2A0B
#define CS4321_MACSEC_EGRESS_STCAM_SA_MAP5		0x2A10
#define CS4321_MACSEC_EGRESS_DEBUG_FIFO_CTRL		0x2A20
#define CS4321_MACSEC_EGRESS_DFF_LEVEL			0x2A22
#define CS4321_MACSEC_EGRESS_DSF_LEVEL			0x2A23
#define CS4321_MACSEC_EGRESS_DCF_LEVEL			0x2A26
#define CS4321_MACSEC_EGRESS_DEBUG_FIFO_THRESHOLD	0x2A27
#define CS4321_MACSEC_EGRESS_DEBUG_FIFO_STATUS		0x2A28
#define CS4321_MACSEC_EGRESS_DEBUG_FIFO_CTX_STATUS	0x2A2A
#define CS4321_MACSEC_EGRESS_SHAPER_DELAY		0x2A2D
#define CS4321_MACSEC_EGRESS_MAIN_INT			0x2A32
#define CS4321_MACSEC_EGRESS_MAIN_INTE			0x2A33
#define CS4321_MACSEC_EGRESS_MAIN_INTS			0x2A34
#define CS4321_MACSEC_EGRESS_FIFOS_INT			0x2A36
#define CS4321_MACSEC_EGRESS_FIFOS_INTE			0x2A37
#define CS4321_MACSEC_EGRESS_FIFOS_INTS			0x2A38
#define CS4321_MACSEC_EGRESS_IP_FIFO_INT		0x2A3A
#define CS4321_MACSEC_EGRESS_IP_FIFO_INTE		0x2A3B
#define CS4321_MACSEC_EGRESS_IP_FIFO_INTS		0x2A3C
#define CS4321_MACSEC_EGRESS_IP_TOKEN_FIFO_INT		0x2A3E
#define CS4321_MACSEC_EGRESS_IP_TOKEN_FIFO_INTE		0x2A3F
#define CS4321_MACSEC_EGRESS_IP_TOKEN_FIFO_INTS		0x2A40
#define CS4321_MACSEC_EGRESS_OP_FIFO_INT		0x2A42
#define CS4321_MACSEC_EGRESS_OP_FIFO_INTE		0x2A43
#define CS4321_MACSEC_EGRESS_OP_FIFO_INTS		0x2A44
#define CS4321_MACSEC_EGRESS_ERR_DROP_FIFO_INT		0x2A46
#define CS4321_MACSEC_EGRESS_ERR_DROP_FIFO_INTE		0x2A47
#define CS4321_MACSEC_EGRESS_ERR_DROP_FIFO_INTS		0x2A48
#define CS4321_MACSEC_EGRESS_PPR_FIFO_INT		0x2A4A
#define CS4321_MACSEC_EGRESS_PPR_FIFO_INTE		0x2A4B
#define CS4321_MACSEC_EGRESS_PPR_FIFO_INTS		0x2A4C
#define CS4321_MACSEC_EGRESS_CTX_MEM_INT		0x2A4E
#define CS4321_MACSEC_EGRESS_CTX_MEM_INTE		0x2A4F
#define CS4321_MACSEC_EGRESS_CTX_MEM_INTS		0x2A50
#define CS4321_MACSEC_EGRESS_DEBUG_FIFO_INT		0x2A52
#define CS4321_MACSEC_EGRESS_DEBUG_FIFO_INTE		0x2A53
#define CS4321_MACSEC_EGRESS_DEBUG_FIFO_INTS		0x2A54
#define CS4321_MACSEC_EGRESS_DEBUG_FIFO_MEM_INT		0x2A56
#define CS4321_MACSEC_EGRESS_DEBUG_FIFO_MEM_INTE	0x2A57
#define CS4321_MACSEC_EGRESS_DEBUG_FIFO_MEM_INTS	0x2A58
#define CS4321_MACSEC_EGRESS_DEBUG_FIFO_CTX_INT		0x2A5A
#define CS4321_MACSEC_EGRESS_DEBUG_FIFO_CTX_INTE	0x2A5B
#define CS4321_MACSEC_EGRESS_DEBUG_FIFO_CTX_INTS	0x2A5C
#define CS4321_MACSEC_EGRESS_TOKEN_MEM_INT		0x2A5E
#define CS4321_MACSEC_EGRESS_TOKEN_MEM_INTE		0x2A5F
#define CS4321_MACSEC_EGRESS_TOKEN_MEM_INTS		0x2A60
#define CS4321_MACSEC_EGRESS_SB_FIFO_INT		0x2A63
#define CS4321_MACSEC_EGRESS_SB_FIFO_INTE		0x2A64
#define CS4321_MACSEC_EGRESS_SB_FIFO_INTS		0x2A65
#define CS4321_MACSEC_EGRESS_CLASSIFIER_ERROR_INT	0x2A67
#define CS4321_MACSEC_EGRESS_CLASSIFIER_ERROR_INTE	0x2A68
#define CS4321_MACSEC_EGRESS_CLASSIFIER_ERROR_INTS	0x2A69
#define CS4321_MACSEC_EGRESS_DF_FIFO_INT		0x2A6B
#define CS4321_MACSEC_EGRESS_DF_FIFO_INTE		0x2A6C
#define CS4321_MACSEC_EGRESS_DF_FIFO_INTS		0x2A6D
#define CS4321_MACSEC_EGRESS_DS_FIFO_INT		0x2A6F
#define CS4321_MACSEC_EGRESS_DS_FIFO_INTE		0x2A70
#define CS4321_MACSEC_EGRESS_DS_FIFO_INTS		0x2A71
#define CS4321_MACSEC_EGRESS_DC_FIFO_INT		0x2A73
#define CS4321_MACSEC_EGRESS_DC_FIFO_INTE		0x2A74
#define CS4321_MACSEC_EGRESS_DC_FIFO_INTS		0x2A75
#define CS4321_MACSEC_EGRESS_SHAPER_FIFO_INT		0x2A77
#define CS4321_MACSEC_EGRESS_SHAPER_FIFO_INTE		0x2A78
#define CS4321_MACSEC_EGRESS_SHAPER_FIFO_INTS		0x2A79
#define CS4321_MACSEC_EGRESS_SA_SWITCH_ENABLE1		0x2A7B
#define CS4321_MACSEC_EGRESS_SA_SWITCH_ENABLE0		0x2A7C
#define CS4321_MACSEC_EGRESS_SA_SWITCH_INT1		0x2A7E
#define CS4321_MACSEC_EGRESS_SA_SWITCH_INT0		0x2A7F
#define CS4321_MACSEC_EGRESS_SA_SWITCH_INT1E		0x2A80
#define CS4321_MACSEC_EGRESS_SA_SWITCH_INT0E		0x2A81
#define CS4321_MACSEC_EGRESS_SA_SWITCH_INT1S		0x2A82
#define CS4321_MACSEC_EGRESS_SA_SWITCH_INT0S		0x2A83
#define CS4321_MAC_LAT_CTRL_RESET			0x3000
#define CS4321_MAC_LAT_CTRL_CONFIG			0x3001
#define CS4321_MAC_LAT_CTRL_INT				0x3005
#define CS4321_MAC_LAT_CTRL_INTE			0x3006
#define CS4321_MAC_LAT_CTRL_INTO			0x3007
#define CS4321_PTP_RX_RESET				0x3100
#define CS4321_PTP_RX_CTRL				0x3101
#define CS4321_PTP_RX_VLAN1				0x3102
#define CS4321_PTP_RX_VLAN2				0x3103
#define CS4321_PTP_RX_VLAN3				0x3104
#define CS4321_PTP_RX_LATENCY1				0x3107
#define CS4321_PTP_RX_LATENCY0				0x3108
#define CS4321_PTP_RX_NPU_EVNT_GEN2			0x310F
#define CS4321_PTP_RX_NPU_EVNT_GEN1			0x3110
#define CS4321_PTP_RX_NPU_EVNT_GEN0			0x3111
#define CS4321_PTP_RX_TW_CTRL				0x3112
#define CS4321_PTP_RX_ENB_AUTO_SYNC			0x3113
#define CS4321_PTP_RX_PERIOD2				0x3114
#define CS4321_PTP_RX_PERIOD1				0x3115
#define CS4321_PTP_RX_PERIOD0				0x3116
#define CS4321_PTP_RX_TIME3				0x3117
#define CS4321_PTP_RX_TIME2				0x3118
#define CS4321_PTP_RX_TIME1				0x3119
#define CS4321_PTP_RX_TIME0				0x311A
#define CS4321_PTP_RX_SUB_NS1				0x311B
#define CS4321_PTP_RX_SUB_NS0				0x311C
#define CS4321_PTP_RX_SEC1				0x311D
#define CS4321_PTP_RX_SEC0				0x311E
#define CS4321_PTP_RX_NS1				0x311F
#define CS4321_PTP_RX_NS0				0x3120
#define CS4321_PTP_RX_SNAPSHOT				0x3121
#define CS4321_PTP_RX_TIME_SNAPSHOT9			0x3122
#define CS4321_PTP_RX_TIME_SNAPSHOT8			0x3123
#define CS4321_PTP_RX_TIME_SNAPSHOT7			0x3124
#define CS4321_PTP_RX_TIME_SNAPSHOT6			0x3125
#define CS4321_PTP_RX_TIME_SNAPSHOT5			0x3126
#define CS4321_PTP_RX_TIME_SNAPSHOT4			0x3127
#define CS4321_PTP_RX_TIME_SNAPSHOT3			0x3128
#define CS4321_PTP_RX_TIME_SNAPSHOT2			0x3129
#define CS4321_PTP_RX_TIME_SNAPSHOT1			0x312A
#define CS4321_PTP_RX_TIME_SNAPSHOT0			0x312B
#define CS4321_PTP_RX_UPDATE_COUNT1			0x312C
#define CS4321_PTP_RX_UPDATE_COUNT0			0x312D
#define CS4321_PTP_RX_PPS_UPDATE_COUNT			0x312E
#define CS4321_PTP_RX_PPS_PHASE1			0x3131
#define CS4321_PTP_RX_PPS_PHASE0			0x3132
#define CS4321_PTP_RX_PPS_FREQ1				0x3133
#define CS4321_PTP_RX_PPS_FREQ0				0x3134
#define CS4321_PTP_RX_PPS_FREQE1			0x3135
#define CS4321_PTP_RX_PPS_FREQE0			0x3136
#define CS4321_PTP_RX_PPS_FREQU_THRES			0x3137
#define CS4321_PTP_RX_INT				0x3138
#define CS4321_PTP_RX_INTE				0x3139
#define CS4321_PTP_RX_INTO				0x313A
#define CS4321_PTP_RX_CLR_DO_NOTHING_FLAG		0x3144
#define CS4321_PTP_TX_RESET				0x3150
#define CS4321_PTP_TX_CTRL				0x3151
#define CS4321_PTP_TX_VLAN1				0x3152
#define CS4321_PTP_TX_VLAN2				0x3153
#define CS4321_PTP_TX_VLAN3				0x3154
#define CS4321_PTP_TX_LATENCY1				0x3157
#define CS4321_PTP_TX_LATENCY0				0x3158
#define CS4321_PTP_TX_NPU_EVNT_GEN2			0x315F
#define CS4321_PTP_TX_NPU_EVNT_GEN1			0x3160
#define CS4321_PTP_TX_NPU_EVNT_GEN0			0x3161
#define CS4321_PTP_TX_TW_CTRL				0x3162
#define CS4321_PTP_TX_ENB_AUTO_SYNC			0x3163
#define CS4321_PTP_TX_PERIOD2				0x3164
#define CS4321_PTP_TX_PERIOD1				0x3165
#define CS4321_PTP_TX_PERIOD0				0x3166
#define CS4321_PTP_TX_TIME3				0x3167
#define CS4321_PTP_TX_TIME2				0x3168
#define CS4321_PTP_TX_TIME1				0x3169
#define CS4321_PTP_TX_TIME0				0x316A
#define CS4321_PTP_TX_SUB_NS1				0x316B
#define CS4321_PTP_TX_SUB_NS0				0x316C
#define CS4321_PTP_TX_SEC1				0x316D
#define CS4321_PTP_TX_SEC0				0x316E
#define CS4321_PTP_TX_NS1				0x316F
#define CS4321_PTP_TX_NS0				0x3170
#define CS4321_PTP_TX_SNAPSHOT				0x3171
#define CS4321_PTP_TX_TIME_SNAPSHOT9			0x3172
#define CS4321_PTP_TX_TIME_SNAPSHOT8			0x3173
#define CS4321_PTP_TX_TIME_SNAPSHOT7			0x3174
#define CS4321_PTP_TX_TIME_SNAPSHOT6			0x3175
#define CS4321_PTP_TX_TIME_SNAPSHOT5			0x3176
#define CS4321_PTP_TX_TIME_SNAPSHOT4			0x3177
#define CS4321_PTP_TX_TIME_SNAPSHOT3			0x3178
#define CS4321_PTP_TX_TIME_SNAPSHOT2			0x3179
#define CS4321_PTP_TX_TIME_SNAPSHOT1			0x317A
#define CS4321_PTP_TX_TIME_SNAPSHOT0			0x317B
#define CS4321_PTP_TX_UPDATE_COUNT1			0x317C
#define CS4321_PTP_TX_UPDATE_COUNT0			0x317D
#define CS4321_PTP_TX_PPS_FREQ1				0x3183
#define CS4321_PTP_TX_PPS_FREQ0				0x3184
#define CS4321_PTP_TX_PPS_FREQE1			0x3185
#define CS4321_PTP_TX_PPS_FREQE0			0x3186
#define CS4321_PTP_TX_PPS_FREQU_THRES			0x3187
#define CS4321_PTP_TX_INT				0x3188
#define CS4321_PTP_TX_INTE				0x3189
#define CS4321_PTP_TX_INTO				0x318A
#define CS4321_PTP_TX_CLR_DO_NOTHING_FLAG		0x3194
#define CS4321_PTP_MISC_MEM_PTR				0x31A1
#define CS4321_PTP_MISC_MEM_ACCESS			0x31A2
#define CS4321_PTP_MISC_MEM_DATA4			0x31A3
#define CS4321_PTP_MISC_MEM_DATA3			0x31A4
#define CS4321_PTP_MISC_MEM_DATA2			0x31A5
#define CS4321_PTP_MISC_MEM_DATA1			0x31A6
#define CS4321_PTP_MISC_MEM_DATA0			0x31A7
#define CS4321_PTP_MISC_MEM_DEPTH			0x31A8
#define CS4321_PTP_MISC_MEM_THRESHOLD			0x31A9
#define CS4321_PTP_MISC_MEM_INT				0x31B0
#define CS4321_PTP_MISC_MEM_INTE			0x31B1
#define CS4321_PTP_MISC_MEM_INTO			0x31B2
#define CS4321_PTP_MISC_INT				0x31B4
#define CS4321_PTP_MISC_INTE				0x31B5
#define CS4321_PTP_MISC_DOMAIN_LOOKUP15			0x31B6
#define CS4321_PTP_MISC_DOMAIN_LOOKUP0			0x31C5
#define CS4321_RADJ_INGRESS_RX_MUXSWAP_CTRL0		0x3200
#define CS4321_RADJ_INGRESS_RX_NRA_MIN_IFG		0x3204
#define CS4321_RADJ_INGRESS_RX_NRA_LEVEL		0x3205
#define CS4321_RADJ_INGRESS_RX_NRA_SETTLE		0x3206
#define CS4321_RADJ_INGRESS_RX_NRA_EXTENT		0x3207
#define CS4321_RADJ_INGRESS_RX_FIFO_CTRL		0x3208
#define CS4321_RADJ_INGRESS_TX_ADD_FILL_DATA1		0x3210
#define CS4321_RADJ_INGRESS_TX_ADD_FILL_DATA0		0x3211
#define CS4321_RADJ_INGRESS_TX_ADD_FILL_CTRL		0x3212
#define CS4321_RADJ_INGRESS_TX_MUXSWAP_CTRL0		0x3213
#define CS4321_RADJ_INGRESS_TX_PRA_MIN_IFG		0x3214
#define CS4321_RADJ_INGRESS_TX_PRA_LEVEL		0x3215
#define CS4321_RADJ_INGRESS_TX_PRA_SETTLE		0x3216
#define CS4321_RADJ_INGRESS_TX_PRA_EXTENT		0x3217
#define CS4321_RADJ_INGRESS_TX_FIFO_CTRL		0x3218
#define CS4321_RADJ_INGRESS_TX_INTERRUPT		0x3219
#define CS4321_RADJ_INGRESS_TX_INTENABLE		0x321A
#define CS4321_RADJ_INGRESS_MISC_RESET			0x3220
#define CS4321_RADJ_EGRESS_RX_NRA_MIN_IFG		0x3284
#define CS4321_RADJ_EGRESS_RX_NRA_LEVEL			0x3285
#define CS4321_RADJ_EGRESS_RX_NRA_SETTLE		0x3286
#define CS4321_RADJ_EGRESS_RX_NRA_EXTENT		0x3287
#define CS4321_RADJ_EGRESS_RX_FIFO_CTRL			0x3288
#define CS4321_RADJ_EGRESS_TX_ADD_FILL_DATA1		0x3290
#define CS4321_RADJ_EGRESS_TX_ADD_FILL_DATA0		0x3291
#define CS4321_RADJ_EGRESS_TX_ADD_FILL_CTRL		0x3292
#define CS4321_RADJ_EGRESS_TX_MUXSWAP_CTRL0		0x3293
#define CS4321_RADJ_EGRESS_TX_PRA_MIN_IFG		0x3294
#define CS4321_RADJ_EGRESS_TX_PRA_LEVEL			0x3295
#define CS4321_RADJ_EGRESS_TX_PRA_SETTLE		0x3296
#define CS4321_RADJ_EGRESS_TX_PRA_EXTENT		0x3297
#define CS4321_RADJ_EGRESS_TX_FIFO_CTRL			0x3298
#define CS4321_RADJ_EGRESS_TX_INTERRUPT			0x3299
#define CS4321_RADJ_EGRESS_TX_INTENABLE			0x329A
#define CS4321_RADJ_EGRESS_MISC_RESET			0x32A0
#define CS4321_EEE_CTRL_INGRESS_INT			0x3319
#define CS4321_EEE_CTRL_INGRESS_INTE			0x331A
#define CS4321_EEE_CTRL_INGRESS_INTO			0x331B
#define CS4321_EEE_CTRL_EGRESS_INT			0x3399
#define CS4321_EEE_CTRL_EGRESS_INTE			0x339A
#define CS4321_EEE_CTRL_EGRESS_INTO			0x339B
#define CS4321_PM_CTRL					0x3400
#define CS4321_PM_CLEAR					0x3401
#define CS4321_PM_INTERRUPT				0x3403
#define CS4321_PM_INTENABLE				0x3404
#define CS4321_PM_STATS_ACCESS				0x3408
#define CS4321_PM_STATS_DATA2				0x3409
#define CS4321_PM_STATS_DATA1				0x340A
#define CS4321_PM_STATS_DATA0				0x340B
#define CS4321_LED_RESET				0x3500
#define CS4321_LED_LED_CTRL				0x3501
#define CS4321_LED_LED_STATUS_DEBUG			0x3503
#define CS4321_LED_CFG_SUSTAIN_DUR			0x3504
#define CS4321_LED_EVENT_CFG_LINK_ACTIVE		0x3505
#define CS4321_LED_EVENT_CFG_LINK_HOST_DIS		0x3506
#define CS4321_LED_EVENT_CFG_MODULE_BOOT		0x3507
#define CS4321_LED_EVENT_CFG_BEACON			0x3508
#define CS4321_LED_EVENT_CFG_TX_FAULT			0x3509
#define CS4321_LED_EVENT_CFG_RX_LOS			0x350A
#define CS4321_LED_EVENT_CFG_MOD_ABS			0x350B
#define CS4321_LED_EVENT_CFG_EDC_CONVERGED		0x350C
#define CS4321_LED_EVENT_CFG_GEN_GPIO			0x350D
#define CS4321_LED_EVENT_CFG_USER_DEF1			0x350E
#define CS4321_LED_EVENT_CFG_USER_DEF2			0x350F
#define CS4321_LED_EVENT_CFG_USER_DEF3			0x3510
#define CS4321_LED_PRIORITY_DEF0			0x3511
#define CS4321_LED_PRIORITY_DEF1			0x3512
#define CS4321_LED_PRIORITY_DEF2			0x3513
#define CS4321_LED_PRIORITY_DEF3			0x3514
#define CS4321_LED_EVENT_CFG_LINK_ACTIVE_B		0x3515
#define CS4321_LED_LED_MODE_SEL				0x3516
#define CS4321_LED_LED_AUTO_LINK_ACTIVE_CFG		0x3517
#define CS4321_LED_LED_AUTO_LINK_ACTIVE_WIN_CFG_A	0x3518
#define CS4321_LED_LED_AUTO_LINK_ACTIVE_INV_CFG_A	0x3519
#define CS4321_LED_LED_AUTO_LINK_ACTIVE_WIN_CFG_B	0x351A
#define CS4321_LED_LED_AUTO_LINK_ACTIVE_INV_CFG_B	0x351B
#define CS4321_EFUSE_GENERAL_STATUS			0x3600
#define CS4321_EFUSE_READ_WRD_OFFSET			0x3604
#define CS4321_EFUSE_READ_START				0x3605
#define CS4321_EFUSE_READ_STATUS			0x3606
#define CS4321_EFUSE_READ_DATA				0x3607
#define CS4321_EFUSE_PDF_MISC_CHIP_CONFIG		0x3616
#define CS4321_EFUSE_PDF_SKU				0x3617
#define CS4321_EFUSE_PDF_VOL_MON_LUT15			0x361F
#define CS4321_EFUSE_PDF_VOL_MON_LUT7			0x3627
#define CS4321_SFP_CACHE_CONFIG_RESET			0x3700
#define CS4321_SFP_CACHE_CONFIG_STATUS			0x3701
#define CS4321_SFP_CACHE_CONFIG_CONFIG_GENERAL		0x3702
#define CS4321_SFP_CACHE_CONFIG_READ_START		0x3703
#define CS4321_SFP_CACHE_CONFIG_CONFIG_DIAG_POLL_INTERVAL 0x3704
#define CS4321_SFP_CACHE_CONFIG_CONFIG_I2C		0x3705
#define CS4321_SFP_CACHE_CONFIG_WRITE_SETUP		0x3708
#define CS4321_SFP_CACHE_CONFIG_WRITE_START		0x3709
#define CS4321_SFP_CACHE_CONFIG_WRITE_STATUS		0x370A
#define CS4321_SFP_CACHE_CONFIG_TBUF_TIME		0x370C
#define CS4321_SFP_CACHE_CONFIG_TSU_TIME		0x370D
#define CS4321_SFP_CACHE_CONFIG_SCL_LOW_TIME		0x370E
#define CS4321_SFP_CACHE_CONFIG_SCL_HIGH_TIME		0x370F
#define CS4321_SFP_CACHE_CONFIG_START_HOLD_TIME		0x3710
#define CS4321_SFP_CACHE_CONFIG_INT			0x3711
#define CS4321_SFP_CACHE_CONFIG_INTE			0x3712
#define CS4321_SFP_CACHE_CONFIG_INTO			0x3713
#define CS4321_SFP_CACHE_CONFIG_INTZ			0x3714
#define CS4321_SFP_CACHE_CONFIG_MOD_ABS_HOLDOFF_CFG	0x3716
#define CS4321_SFP_CACHE_CONFIG_MODULE_MODE_SELECT	0x3717
#define CS4321_SFP_CACHE_CONFIG_QSFP_CONFIG		0x3718
#define CS4321_SFP_CACHE_CONFIG_QSFP_HIGH_PAGES_HOLDOFF	0x3719
#define CS4321_SFP_CACHE_CONFIG_QSFP_STATUS		0x371a
#define CS4321_SFP_CACHE_CONFIG_QSFP_READ_START		0x371b
#define CS4321_SFP_CACHE_CONFIG_ALARM_CFG		0x3721
#define CS4321_SFP_CACHE_CONFIG_ALARM_MASK9		0x3722
#define CS4321_SFP_CACHE_CONFIG_ALARM_MASK8		0x3723
#define CS4321_SFP_CACHE_CONFIG_ALARM_MASK7		0x3724
#define CS4321_SFP_CACHE_CONFIG_ALARM_MASK6		0x3725
#define CS4321_SFP_CACHE_CONFIG_ALARM_MASK5		0x3726
#define CS4321_SFP_CACHE_CONFIG_ALARM_MASK4		0x3727
#define CS4321_SFP_CACHE_CONFIG_ALARM_MASK3		0x3728
#define CS4321_SFP_CACHE_CONFIG_ALARM_MASK2		0x3729
#define CS4321_SFP_CACHE_CONFIG_ALARM_MASK1		0x372A
#define CS4321_SFP_CACHE_CONFIG_ALARM_MASK0		0x372B
#define CS4321_SFP_CACHE_CONFIG_ALARM_INT		0x372C
#define CS4321_SFP_CACHE_CONFIG_ALARM_INTE		0x372D
#define CS4321_SFP_CACHE_CONFIG_ALARM_INTO		0x372E
#define CS4321_SFP_CACHE_CONFIG_ALARM_INTZ		0x372F
#define CS4321_SFP_CACHE_MODDEF_CACHE			0x3800
#define CS4321_SFP_CACHE_DIAG_CACHE			0x3900
#define CS4321_FRACDIV_RESET				0x3A00
#define CS4321_FRACDIV_EN				0x3A01
#define CS4321_FRACDIV_NUMERATOR0			0x3A02
#define CS4321_FRACDIV_NUMERATOR1			0x3A03
#define CS4321_FRACDIV_WIDTH				0x3A04
#define CS4321_FRACDIV_INTDIV				0x3A05
#define CS4321_FRACDIV_STAGE1_EN			0x3A06
#define CS4321_FRACDIV_STAGE2_EN			0x3A07
#define CS4321_FRACDIV_STAGE1PRELOAD0			0x3A08
#define CS4321_FRACDIV_STAGE1PRELOAD1			0x3A09
#define CS4321_FRACDIV_STAGE2PRELOAD0			0x3A0A
#define CS4321_FRACDIV_STAGE2PRELOAD1			0x3A0B
#define CS4321_FRACDIV_CLKCTRL				0x3A0C
#define CS4321_FRACDIV_DITHER_EN			0x3A0D
#define CS4321_FRACDIV_DITHER_SEL			0x3A0E
#define CS4321_PBERT_INGRESS_PBERT_TX_MODE		0x3B00
#define CS4321_PBERT_INGRESS_PBERT_TX_PROTOCOL		0x3B01
#define CS4321_PBERT_INGRESS_PBERT_TX_PCTRL_FR		0x3B02
#define CS4321_PBERT_INGRESS_PBERT_TX_PCTRL_OS0		0x3B03
#define CS4321_PBERT_INGRESS_PBERT_TX_FPAT01		0x3B05
#define CS4321_PBERT_INGRESS_PBERT_TX_FPAT23		0x3B06
#define CS4321_PBERT_INGRESS_PBERT_TX_ULEN		0x3B09
#define CS4321_PBERT_INGRESS_PBERT_TX_ULENMIN		0x3B0A
#define CS4321_PBERT_INGRESS_PBERT_TX_ULENMAX		0x3B0B
#define CS4321_PBERT_INGRESS_PBERT_TX_IFG		0x3B0C
#define CS4321_PBERT_INGRESS_PBERT_TX_UCTRL		0x3B10
#define CS4321_PBERT_INGRESS_PBERT_TX_ERRINS		0x3B11
#define CS4321_PBERT_INGRESS_PBERT_TX_GO		0x3B12
#define CS4321_PBERT_INGRESS_PBERT_TX_UCNT2		0x3B13
#define CS4321_PBERT_INGRESS_PBERT_TX_UOCNT2		0x3B16
#define CS4321_PBERT_INGRESS_PBERT_TX_INTERRUPT		0x3B19
#define CS4321_PBERT_INGRESS_PBERT_TX_DA0		0x3B1C
#define CS4321_PBERT_INGRESS_PBERT_TX_SA0		0x3B1F
#define CS4321_PBERT_INGRESS_PBERT_TX_CUSTOMCFG		0x3B22
#define CS4321_PBERT_INGRESS_PBERT_TX_CUSTOMFRAME_ACCESS 0x3B23
#define CS4321_PBERT_INGRESS_PBERT_TX_CUSTOMFRAME_DATA	0x3B24
#define CS4321_PBERT_INGRESS_PBERT_TX_CUSTOMFRAMEFCS0	0x3B25
#define CS4321_PBERT_INGRESS_PBERT_RX_MODE		0x3B40
#define CS4321_PBERT_INGRESS_PBERT_RX_PROTOCOL		0x3B41
#define CS4321_PBERT_INGRESS_PBERT_RX_PCTRL_FR		0x3B42
#define CS4321_PBERT_INGRESS_PBERT_RX_PCTRL_OS0		0x3B43
#define CS4321_PBERT_INGRESS_PBERT_RX_FPAT01		0x3B45
#define CS4321_PBERT_INGRESS_PBERT_RX_UGOODCNT2		0x3B4C
#define CS4321_PBERT_INGRESS_PBERT_RX_UOGOODCNT2	0x3B4F
#define CS4321_PBERT_INGRESS_PBERT_RX_UERRCNT2		0x3B52
#define CS4321_PBERT_INGRESS_PBERT_RX_UOERRCNT2		0x3B55
#define CS4321_PBERT_INGRESS_PBERT_RX_PRBSERRCNT2	0x3B58
#define CS4321_PBERT_INGRESS_PBERT_RX_INTERRUPT		0x3B5C
#define CS4321_PBERT_INGRESS_PBERT_RX_DA0		0x3B62
#define CS4321_PBERT_INGRESS_PBERT_RX_SA0		0x3B65
#define CS4321_PBERT_EGRESS_PBERT_TX_MODE		0x3B80
#define CS4321_PBERT_EGRESS_PBERT_TX_PROTOCOL		0x3B81
#define CS4321_PBERT_EGRESS_PBERT_TX_PCTRL_FR		0x3B82
#define CS4321_PBERT_EGRESS_PBERT_TX_PCTRL_OS0		0x3B83
#define CS4321_PBERT_EGRESS_PBERT_TX_FPAT01		0x3B85
#define CS4321_PBERT_EGRESS_PBERT_TX_FPAT23		0x3B86
#define CS4321_PBERT_EGRESS_PBERT_TX_ULEN		0x3B89
#define CS4321_PBERT_EGRESS_PBERT_TX_ULENMIN		0x3B8A
#define CS4321_PBERT_EGRESS_PBERT_TX_ULENMAX		0x3B8B
#define CS4321_PBERT_EGRESS_PBERT_TX_IFG		0x3B8C
#define CS4321_PBERT_EGRESS_PBERT_TX_UCTRL		0x3B90
#define CS4321_PBERT_EGRESS_PBERT_TX_ERRINS		0x3B91
#define CS4321_PBERT_EGRESS_PBERT_TX_GO			0x3B92
#define CS4321_PBERT_EGRESS_PBERT_TX_UCNT2		0x3B93
#define CS4321_PBERT_EGRESS_PBERT_TX_UOCNT2		0x3B96
#define CS4321_PBERT_EGRESS_PBERT_TX_INTERRUPT		0x3B99
#define CS4321_PBERT_EGRESS_PBERT_TX_DA0		0x3B9C
#define CS4321_PBERT_EGRESS_PBERT_TX_SA0		0x3B9F
#define CS4321_PBERT_EGRESS_PBERT_TX_CUSTOMCFG		0x3BA2
#define CS4321_PBERT_EGRESS_PBERT_TX_CUSTOMFRAME_ACCESS 0x3BA3
#define CS4321_PBERT_EGRESS_PBERT_TX_CUSTOMFRAME_DATA	0x3BA4
#define CS4321_PBERT_EGRESS_PBERT_TX_CUSTOMFRAMEFCS0	0x3BA5
#define CS4321_PBERT_EGRESS_PBERT_RX_MODE		0x3BC0
#define CS4321_PBERT_EGRESS_PBERT_RX_PROTOCOL		0x3BC1
#define CS4321_PBERT_EGRESS_PBERT_RX_PCTRL_FR		0x3BC2
#define CS4321_PBERT_EGRESS_PBERT_RX_PCTRL_OS0		0x3BC3
#define CS4321_PBERT_EGRESS_PBERT_RX_FPAT01		0x3BC5
#define CS4321_PBERT_EGRESS_PBERT_RX_UGOODCNT2		0x3BCC
#define CS4321_PBERT_EGRESS_PBERT_RX_UOGOODCNT2		0x3BCF
#define CS4321_PBERT_EGRESS_PBERT_RX_UERRCNT2		0x3BD2
#define CS4321_PBERT_EGRESS_PBERT_RX_UOERRCNT2		0x3BD5
#define CS4321_PBERT_EGRESS_PBERT_RX_PRBSERRCNT2	0x3BD8
#define CS4321_PBERT_EGRESS_PBERT_RX_INTERRUPT		0x3BDC
#define CS4321_PBERT_EGRESS_PBERT_RX_DA0		0x3BE2
#define CS4321_PBERT_EGRESS_PBERT_RX_SA0		0x3BE5
#define CS4321_EMDS_LINE_RESET				0x3C00
#define CS4321_EMDS_LINE_CONTROL			0x3C01
#define CS4321_EMDS_LINE_STATUS				0x3C02
#define CS4321_EMDS_LINE_SAMPLE_LOAD_NEXT		0x3C04
#define CS4321_EMDS_LINE_SAMPLE_ERR_CNT2		0x3C05
#define CS4321_EMDS_LINE_ALIGNER_CFG_GENERAL		0x3C0B
#define CS4321_EMDS_LINE_ALIGNER_CFG_THRESH		0x3C0C
#define CS4321_EMDS_LINE_VOLTAGE_CFG1			0x3C0D
#define CS4321_EMDS_LINE_VOLTAGE_CFG2			0x3C0E
#define CS4321_EMDS_LINE_PHASE_CFG1			0x3C0F
#define CS4321_EMDS_LINE_PHASE_CFG2			0x3C10
#define CS4321_EMDS_LINE_SETTLE_TIME			0x3C14
#define CS4321_EMDS_HOST_RESET				0x3C80
#define CS4321_EMDS_HOST_CONTROL			0x3C81
#define CS4321_EMDS_HOST_STATUS				0x3C82
#define CS4321_EMDS_HOST_SAMPLE_LOAD_NEXT		0x3C84
#define CS4321_EMDS_HOST_SAMPLE_ERR_CNT2		0x3C85
#define CS4321_EMDS_HOST_ALIGNER_CFG_GENERAL		0x3C8B
#define CS4321_EMDS_HOST_ALIGNER_CFG_THRESH		0x3C8C
#define CS4321_EMDS_HOST_VOLTAGE_CFG1			0x3C8D
#define CS4321_EMDS_HOST_VOLTAGE_CFG2			0x3C8E
#define CS4321_EMDS_HOST_PHASE_CFG1			0x3C8F
#define CS4321_EMDS_HOST_PHASE_CFG2			0x3C90
#define CS4321_EMDS_HOST_SETTLE_TIME			0x3C94
#define CS4321_OMS_INGRESS_RESET			0x3E80
#define CS4321_OMS_INGRESS_CONTROL_VALID_0		0x3E81
#define CS4321_OMS_INGRESS_CONTROL_VALID_1		0x3E82
#define CS4321_OMS_INGRESS_CONTROL_0_DA2		0x3E83
#define CS4321_OMS_INGRESS_CONTROL_0_ET			0x3E9B
#define CS4321_OMS_INGRESS_CONTROL_DA_RANGE_LOW2	0x3EA3
#define CS4321_OMS_INGRESS_CONTROL_DA_RANGE_HIGH2	0x3EA6
#define CS4321_OMS_INGRESS_CONTROL_0_DA_ET3		0x3EA9
#define CS4321_OMS_INGRESS_CONTROL_1_DA_ET3		0x3EAD
#define CS4321_OMS_INGRESS_TAG_CONTROL			0x3EB1
#define CS4321_OMS_INGRESS_R802DOT1Q_TAG_MAP1		0x3EB2
#define CS4321_OMS_INGRESS_R802DOT1S_TAG_ET0		0x3EB4
#define CS4321_OMS_INGRESS_R802DOT1S_TAG_ET1		0x3EB5
#define CS4321_OMS_INGRESS_R802DOT1S_TAG_ET2		0x3EB6
#define CS4321_OMS_EGRESS_RESET				0x3EC0
#define CS4321_OMS_EGRESS_CONTROL_VALID_0		0x3EC1
#define CS4321_OMS_EGRESS_CONTROL_VALID_1		0x3EC2
#define CS4321_OMS_EGRESS_CONTROL_0_DA2			0x3EC3
#define CS4321_OMS_EGRESS_CONTROL_0_ET			0x3EDB
#define CS4321_OMS_EGRESS_CONTROL_DA_RANGE_LOW2		0x3EE3
#define CS4321_OMS_EGRESS_CONTROL_DA_RANGE_HIGH2	0x3EE6
#define CS4321_OMS_EGRESS_CONTROL_0_DA_ET3		0x3EE9
#define CS4321_OMS_EGRESS_CONTROL_1_DA_ET3		0x3EED
#define CS4321_OMS_EGRESS_TAG_CONTROL			0x3EF1
#define CS4321_OMS_EGRESS_R802DOT1Q_TAG_MAP1		0x3EF2
#define CS4321_OMS_EGRESS_R802DOT1S_TAG_ET0		0x3EF4
#define CS4321_OMS_EGRESS_R802DOT1S_TAG_ET1		0x3EF5
#define CS4321_OMS_EGRESS_R802DOT1S_TAG_ET2		0x3EF6
#define CS4321_EEPROM_LOADER_CONTROL			0x3F00
#define CS4321_EEPROM_LOADER_STATUS			0x3F01
#define CS4321_EEPROM_UNSTICKER_CONTROL			0x3F04

/* Hardware revision numbers for the ASIC */
#define CS4321_HW_REVA 1
#define CS4321_HW_REVB 2

#define CS4321_ID_LSB					0x23E5
#define CS4321_ID_MSB_REVA				0x1002
#define CS4321_ID_MSB_REVB				0x2002
/**
 * Accumulator width options for the Fractional-N divider.
 */
enum {
	CS4321_FRACDIV_ACCUM_WIDTH_8BIT = 0,	/** 8 bit accumulator */
	CS4321_FRACDIV_ACCUM_WIDTH_16BIT = 1,	/** 16 bit accumulator */
	CS4321_FRACDIV_ACCUM_WIDTH_24BIT = 2,	/** 24 bit accumulator */
	CS4321_FRACDIV_ACCUM_WIDTH_32BIT = 3,	/** 32 bit accumulator */
} cs4321_fracdiv_accumulator_width;

/**
 * Select the polynomial used for dithering in the
 * Fractional Divider
 */
enum {
	CS4321_FRACDIV_2EXP8_MINUS1 = 0,	/** 2^8 - 1 */
	CS4321_FRACDIV_2EXP16_MINUS1 = 1,	/** 2^16 - 1 */
	CS4321_FRACDIV_2EXP24_MINUS1 = 2,	/** 2^24 - 1 */
	CS4321_FRACDIV_2EXP32_MINUS1 = 3,	/** 2^32 - 1 */
} cs4321_fracdiv_dither_polynomial;
